Several of today's computer system architectures employ a source strobed bus and method to transfer data between devices. In a typical source strobe architecture, the transmitting device transmits to the receiving device a clock signal/strobe and data. The strobe alerts the receiving device that valid data has been transmitted over the bus. Computer bus architectures such as AGP (accelerated graphics port), DDR SDRAM (double data rate synchronous dynamic random access memory), and RDRAM (Rambus random access memory) utilize source strobes in this manner.
A source strobe data bus is an efficient mechanism for transferring large amounts of data on a minimum number of pins or connections between devices. In the typical source strobe computer architecture, one device connected to the source strobed bus continuously serves as a bus master while the other devices continuously serve as bus slaves. In this type of architecture, the master always controls access to the source strobed bus. Thus, the typical source strobed bus would not require bus arbitration since the same bus master is always in control of the bus.
It is desirable, however, to extend a source strobed bus computer architecture to allow for multiple or different devices to become the master of the bus. That is, instead of appointing one device as the continuous bus master, each device connected to the bus will have the opportunity to request and become the master of the bus at some point in time. By allowing any one of multiple devices to serve as a bus master, however, would require an arbitration scheme to decide which device has control of the source strobed bus at a given time. Typical arbitration schemes involve the use of a separate dedicated arbitration device whose sole responsibility is to arbitrate control of the bus between the other devices connected to the bus. This dedicated arbitration device adds expense and delays to the system since an additional device is connected to, and communicating over, the bus. Thus, there is a desire and need to implement an arbitration method in a source strobed bus architecture that does not use a separate dedicated arbitration device and that allows any device connected to the bus to become the bus master.